Efficient reduction of electromagnetic emission in LIN driver

ABSTRACT

A Local Interconnect Network (LIN) driver circuit employs a charging/discharging current applied to the gate of a driver transistor coupled to an LIN bus. The charging current includes a constant charging current and an additional soft charging current, whereas the discharging current includes a constant discharging current and an additional soft discharging current. As a result of the soft charge/discharge components, there is a significant reduction in electromagnetic emission on the LIN bus.

PRIORITY CLAIM

This application claims priority from Chinese Application for Patent No.201110461475.7 filed Dec. 30, 2011, the disclosure of which isincorporated by reference.

BACKGROUND

1. Technical Field

The present invention relates generally to Local Interconnect Network(LIN) circuitry and, more specifically, to reducing electromagneticemission in an integrated LIN driver.

2. Introduction

Industry specifications for LIN drivers typically mandate that atransmitted signal be shaped with a predefined slope in order to reduceelectromagnetic emission at high frequencies. Unfortunately, therequested small slope oftentimes results in an invalid duty cycle, whichconsequently results in an error in data transmission. In an attempt tosolve this issue, many conventional LIN drivers employ a step current asa gate charging/discharging current. However, the sharp edges of thestep current contribute to a significant level of radiated emission onthe LIN bus. Therefore, there exists a need for an LIN driver operableto ensure signal integrity while achieving reduced electromagneticemission on the LIN bus.

SUMMARY

The present disclosure provides an integrated LIN driver having reducedelectromagnetic emission. One embodiment provides a driver circuitcomprising: a driver transistor having a gate terminal; a first circuitoperable in response to a first phase of a clock signal to generate agate charging current for application to the gate terminal; and a secondcircuit operable in response to a second phase of the clock signal togenerate a gate discharging current for application to the gateterminal; wherein said gate charging current comprises a sum of a firstexponentially decreasing current and a first constant current; andwherein said gate discharging current comprises a sum of a secondexponentially decreasing current and a second constant current.

In another embodiment, the LIN driver circuit comprises: chargingcircuitry operable to receive a first charging current and generate asecond charging current; discharging circuitry operable to receive afirst discharging current and generate a second discharging current; andan output transistor operable to receive a gate current, wherein duringa charging phase, said gate current comprises said first chargingcurrent and said second charging current, and wherein during adischarging phase, said gate current comprises said first dischargingcurrent and said second discharging current; wherein during saidcharging phase, said second charging current dissipates such that saidgate current substantially comprises said first charging current; andwherein during said discharging phase, said second discharging currentdissipates such that said gate current substantially comprises saidfirst discharging current.

Yet another embodiment of the present disclosure provides a drivercircuit comprising: a driver transistor having a gate terminal; a firstcircuit comprising a first capacitor coupled to a first transistor and afirst switch, said first circuit operable to receive a first constantcurrent and generate a first exponentially decreasing current; a secondswitch operable to couple said first circuit to said gate terminal toapply a gate charging current to said gate terminal; a second circuitcoupled to said gate terminal, said second circuit comprising a thirdswitch and a second capacitor, said second circuit operable to generatea second exponentially decreasing current; and a fourth switch coupledto said gate terminal and said second circuitry, wherein said third andfourth switches are operable to apply a gate discharging current to saidgate terminal; wherein said gate charging current comprises a sum ofsaid first exponentially decreasing current and said first constantcurrent; and wherein said gate discharging current comprises a sum ofsaid second exponentially decreasing current and a second constantcurrent.

Another embodiment of the present disclosure provides a method forreducing electromagnetic emission in a driver circuit, the methodcomprising: generating a first exponentially decreasing current inresponse to a first phase of a clock signal; generating a secondexponentially decreasing current in response to a second phase of theclock signal; applying a charging current at a gate terminal of a drivertransistor, wherein said charging current comprises a sum of a firstconstant current and said first exponentially decreasing current; andapplying a discharging current at said gate terminal of said drivertransistor, wherein said discharging current comprises a sum of a secondconstant current and said second exponentially decreasing current.

The foregoing and other features and advantages of the presentdisclosure will become further apparent from the following detaileddescription of the embodiments, read in conjunction with theaccompanying drawings. The detailed description and drawings are merelyillustrative of the disclosure, rather than limiting the scope of theinvention as defined by the appended claims and equivalents thereof.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments are illustrated by way of example in the accompanyingfigures not necessarily drawn to scale, in which like reference numbersindicate similar parts, and in which:

FIGS. 1A and 1B illustrate an example embodiment of a conventional LINdriver circuit and the timing diagram and waveforms corresponding to theconventional LIN driver circuit;

FIGS. 2A and 2B illustrate an LIN driver circuit in accordance with anembodiment of the present disclosure and the timing diagram andwaveforms corresponding to the disclosed LIN driver circuit; and

FIG. 3 illustrates a comparison of LIN emission simulation results forthe LIN driver circuits shown in FIGS. 1A and 2A.

DETAILED DESCRIPTION OF THE DRAWINGS

Reference is made to FIGS. 1A and 1B, wherein an example embodiment of aconventional LIN driver circuit 100 is shown in FIG. 1A, and isdiscussed herein in combination with its corresponding timing diagramand waveforms 150 illustrated in FIG. 1B. The conventional LIN drivercircuit 100 comprises a reference current source 102 supplying referencecurrent I_(R) to a first current mirror 104, comprised of transistors M1and M2. Transistor M1 may be sized to transistor M2 to set mirroredreference current I_(R)′, which is supplied to a second current mirror206 comprised of transistors M3, M4, and M5. Transistor M4 may be sizedrelative to transistor M3 to set a constant charge current I₁, which isoperably connected to the gate of a transistor MD operating as a lowside driver by a switch S₁ operating on a phase of a first clock signalΦ₁. Transistor M5 may be sized relative to transistor M3 to set anadditional charge current I₁′, which is operably connected to the gateof the driver transistor MD by a second switch S₂ operating on a secondclock signal Φ₁′. In an example embodiment of the circuit 100illustrated in FIG. 1A, I_(R)=5 uA, I_(R)′=10 uA, I₁=20 uA, and I₁′=7uA.

Also included in the first current mirror 104 are transistors M6 and M7.Transistor M6 may be sized relative to transistor M1 to set a constantdischarging current I₂, which is operably connected to the gate of thedriver transistor MD by a third switch S₃ operating on an opposite phaseof the first clock signal Φ₁. Transistor M7 may be sized relative totransistor M2 to set an additional discharge current I₂′, which isoperably connected to the gate of the driver 108 by a fourth switch S₄operating on a third clock signal Φ₁″. In an example embodiment of thecircuit 100 illustrated in FIG. 1A, I₂=20 uA and I₂′=40 uA.

The LIN driver circuit 100 also includes resistor R₁, as well ascapacitor C₀ coupled in parallel with series connected transistor M8 andresistor R₂, which are coupled to the gate of the driver transistor MD.Capacitor C₀ is provided to absorb EMC gate coupling of the drivertransistor MD, and is also used with resistor R₁ to smooth gate chargeand discharge of the driver transistor MD. Transistor M8 operates withthe driver transistor MD to provide a current mirror, wherein theresistor R₂ is provided to adjust the mirror factor. In an exampleembodiment of the circuit 100 illustrated in FIG. 1A, C₀=20 pF.

The source of the driver transistor MD is coupled to the LIN bus 108 viaa first blocking diode D₁ operable to block current flowing into the LINbus 108 from ground. The driver circuit 100 also includes a secondblocking diode D₂ and pull-up resistor R₃ coupled between a supplyvoltage VS and the LIN bus 108, wherein the second blocking diode D₂operates to block current from the LIN bus 108 from reaching the voltagesupply VS.

The conventional LIN driver 100 employs step current I_(GATE) as a gatecharging/discharging current for the driving transistor MD. In order toachieve the step current I_(GATE), two constant currents areintermittently switched on and off, thereby switching between theconstant charging current I₁ and the constant discharging current I₂applied to the gate of MD as step current I_(GATE). As shown in FIG. 1B,phase clock signal Φ₁ is high during the charging phase and low duringthe discharging phase. Accordingly, charging current I₁ is switched on(i.e., applied to the gate of MD) during the charging phase (when Φ₁ ishigh), and is switched off during the discharging phase (when Φ₁ islow). Conversely, discharging current I₂ is switched off during thecharging phase, and is switched on during the discharging phase.

During initial periods of the respective charging and dischargingphases, an additional current is switched on to reduce turn-on/off delaytime of the driver transistor MD. As illustrated by the timing diagramand waveforms 150 illustrated in FIG. 1B, during the initial period of acharging phase, phase clock signal Φ₁′ is high and additional chargingcurrent I₁′ is switched on. Therefore, when Φ₁ and Φ₁′ are high, bothcharging current I₁ and additional charging current I₁′ are applied tothe gate of the driver transistor MD. In other words, when Φ₁ and Φ₁′are high, the step current I_(GATE) is the sum of charging current I₁and additional charging current I₁′. When Φ₁′ goes low and Φ₁ remainshigh, the additional charging current I₁′ is switched off and only thecharging current I₁ is applied to the gate of the driver transistor MD(i.e., I_(GATE)=I₁). During the initial period of a discharging phase,phase clock signal Φ₁″ is high and Φ₁ is low (Φ₁(bar) is high), bothdischarging current I₂ and additional discharging current I₂′ areswitched on (i.e., I_(GATE)=I₂+I₂′). When Φ₁″ goes low and Φ₁ is low,additional discharging current I₂′ is switched off and only dischargingcurrent I₂ is applied to the gate of MD (i.e., I_(GATE)=I₂).Accordingly, the circuit 100 in FIG. 1A produces a step gate currentI_(GATE) having sharp edges 160 caused by switching off the additionalcharging/discharging currents I₁′/I₂′ responsive to the switching ofadditional phase clock signals Φ₁′ and Φ₁″. The step gate currentI_(GATE) is applied to the gate of transistor MD to produce the LIN bussignal 165 shown in FIG. 1B. The embodiment illustrated in FIGS. 1A and1B produces satisfactory duty cycle with the shortened delay time,however, performance of radiated emission on the LIN bus is stronglydegraded due to the sharp edges 160 in the step current I_(GATE).

FIG. 2A illustrates an LIN driver circuit 200 in accordance with anexample embodiment of the present disclosure. The disclosed LIN drivercircuit 200 comprises a reference current source 202 supplying referencecurrent I_(R) to a first current mirror 204, comprised of transistorsM11, M12, and M13. Transistor M11 may be sized to transistor M12 to setmirrored reference current I_(R)′, which is supplied to a second currentmirror 206 comprised of transistors M14 and M15. Transistor M15 may besized relative to transistor M14 to set a constant charge current I₁,and transistor M13 may be sized relative to transistor M11 to set aconstant discharge current I₂. In an example embodiment of the circuit200 illustrated in FIG. 2A, I_(R)=5 uA, I_(R)′=10 uA, I₁=20 uA, andI₂=20 uA.

Coupled to the second current mirror 206 is charging circuitry 210. Thecharging circuitry 210 comprises a switch 212 operating on an oppositephase of a clock signal Φ₁, and a diode connected transistor 214 coupledin parallel with series connected capacitor C₁ and resistor R_(C). Thecharging circuitry 210 and second current mirror 206 are coupled viaswitch 216 to the gate of a transistor MD operating as a low sidedriver, wherein switch 216 operates on a phase of the clock signal Φ₁.

Discharging circuitry 220 is coupled to the first current mirror 204 byswitch 218 operating on the opposite phase of the clock signal Φ₁. Thedischarging circuitry 220 comprises a switch 222 coupled in series witha second capacitor C₂ and resistor R_(D), wherein switch 222 operates onthe opposite phase of the clock signal Φ₁.

The disclosed LIN driver circuit 200 also includes resistor R₁, as wellas capacitor C₀ coupled in parallel with series connected transistor M16and resistor R₂, which are coupled to the gate of the driver transistorMD. As mentioned above, capacitor C₀ is provided to absorb EMC gatecoupling of the driver transistor MD, and is also used with resistor R₁to smooth gate charge and discharge of the driver transistor MD.Transistor M16 operates with the driver transistor MD to provide acurrent mirror, wherein the resistor R₂ is provided to adjust the mirrorfactor. In an example embodiment of the circuit 200 illustrated in FIG.2A, C₀=20 pF.

The source of the driver transistor MD is coupled to the LIN bus 230 viaa first blocking diode D₁ operable to block current flowing into the LINbus 230 from ground. The driver circuit 200 also includes a secondblocking diode D₂ and pull-up resistor R₃ coupled between a supplyvoltage VS and the LIN bus 230, wherein the second blocking diode D₂operates to block current from the LIN bus 230 from reaching the voltagesupply VS.

The LIN driver circuit 200 illustrated in FIG. 2A is similar to thatshown in FIG. 1A in that the LIN driver circuit 200 employs acharging/discharging current I_(GATE2) applied to the gate of the drivertransistor MD coupled to the LIN bus 230. Like the LIN driver circuit100 in FIG. 1A, the LIN driver circuit 200 achieves satisfactory dutycycle by shortening delay time. However, when compared to the LIN drivercircuit 100 in FIG. 1A, the LIN driver circuit 200 illustrated in FIG.2A provides a significant reduction in electromagnetic emission byreplacing the sharp edges 160 shown in FIG. 1B, with a smooth, step-lesscurrent change as shown by the timing diagram and waveforms 250illustrated in FIG. 2B.

In order to achieve the current I_(GATE2), charging and dischargingcurrents are intermittently switched on and off, thereby switchingbetween a charging current and a discharging current applied to the gateof MD as gate current I_(GATE2). During a charging phase, the gatecurrent I_(GATE2) initially comprises the sum of the constant chargecurrent I₁ and an additional soft charge current I₁′. During adischarging phase, the gate current I_(GATE2) initially comprises thesum of the constant discharge current I₂ and an additional softdischarge current I₂′. The charging and discharging phases are describedin greater detail below with reference to the timing diagram andwaveforms 250 illustrated in FIG. 2B.

The phase clock signal Φ₁ represents the charging/discharging phases,wherein Φ₁ is high during the charging phase and low during thedischarging phase. Accordingly, charging currents I₁ and I₁′ areswitched on (i.e., applied to the gate of MD) during the charging phase(when Φ₁ is high), and are switched off during the discharging phase(when Φ₁ is low). Conversely, discharging currents I₂ and I₂′ areswitched off during the charging phase, and are switched on during thedischarging phase.

Referring again to the circuit 200 illustrated in FIG. 2A, additionalsoft charging current I₁′ is provided by charging circuitry 210. Duringthe gate discharging phase (when Φ₁ is low), switch 212 closes andcapacitor C₁ is charged by the constant charge current I₁ to voltageV_(GS). During the charging phase (when Φ₁ is high), switch 216 closes(and switch 212 opens) and the charge stored on capacitor C₁ istransferred as the additional soft charge current I₁′ to the gate of MD(along with charge current I₁). Accordingly, during the charging phase,gate current I_(GATE2) is comprised of the sum of constant chargecurrent I₁ and additional soft charge current I₁′. As the charge on thecapacitor C₁ dissipates, additional soft charge current I₁′ decreasesexponentially until the gate current I_(GATE2) is essentially comprisedof only constant charge current I₁, thus smoothly transitioning from alarger initial charge current (I₁+I₁′) to the constant charge currentI₁. The larger initial charge current reduces the turn-on delay time ofthe driver transistor MD, whereas the smooth exponential transition,shown in FIG. 2B as curve 260, reduces the sharp edges of the gatecurrent I_(GATE2), thereby resulting in decreased electromagneticemission on the LIN bus 230. In an example embodiment of the circuit 200illustrated in FIG. 2A, C₁=10 pF, I₁=20 uA, and I₁′=220 uA (peak).

Additional soft discharging current I₂′ is provided by dischargingcircuitry 220. During the discharging phase, switches 218 and 222 closeand second capacitor C₂ charges to produce the additional softdischarging current I₂′ sunk from the gate of MD with constantdischarging current I₂. Accordingly, during the discharging phase, gatecurrent I_(GATE2) is initially comprised of the sum of constantdischarge current I₂ and additional soft discharge current I₂′. As thecharge on the second capacitor C₂ increases exponentially, additionalsoft discharge current I₂′ exponentially decreases until the gatecurrent I_(GATE2) is essentially comprised of only constant dischargecurrent I₂, thus smoothly transitioning from a larger initial dischargecurrent (I₂+I₂′) to the constant discharge current I₂. The largerinitial discharge current reduces the turn-off delay time of the drivertransistor MD, whereas the smooth exponential transition, shown in FIG.2B as curve 265, reduces the sharp edges of the gate current I_(GATE2),thereby resulting in decreased electromagnetic emission on the LIN bus.In an example embodiment of the circuit 200 illustrated in FIG. 2A,C₂=15 pF, I₂=20 uA, and I₂′=350 uA (peak).

When compared to the conventional LIN driver circuit 100, the disclosedLIN driver 200 provides several advantages including, but not limitedto, a) reduced emission degradation of the LIN output, and b) reducedelectromagnetic emission on the LIN bus. The disclosed LIN drivercircuit 200 eliminates the need for the two additional phase clocksignals Φ₁′ and Φ₁″ of FIG. 1A, thereby eliminating emission degradationof the LIN output caused by the spread of clock timing. Additionally,the smooth charge/discharge current comprising the gate currentI_(GATE2) provides for reduced electromagnetic emission on the LIN bus230 as illustrated by the simulation results 300 provided in FIG. 3.

The simulation results 300 provided in FIG. 3 compare electromagneticemission on the LIN bus for the circuit 100 illustrated in FIG. 1A (thiselectromagnetic emission is identified in FIG. 3 as element 305) withelectromagnetic emission on the LIN bus for the circuit 200 illustratedin FIG. 2A (this electromagnetic emission is identified in FIG. 3 aselement 310). The simulation results 300 illustrate a reduction of up to17 dBuV in electromagnetic emission on the LIN bus 230 of the circuit200 illustrated in FIG. 2A, particularly for frequencies ranging from 1MHz to 10 MHz. As such, the disclosed LIN driver circuit 200 achievessatisfactory duty cycle by shortening delay time while providing asignificant reduction in electromagnetic emission by employing a smooth,step-less gate current.

It should be appreciated by one of ordinary skill in the art that theembodiment disclosed herein is provided to illustrate one example forimplementing an LIN driver circuit in accordance with the presentdisclosure. As such, variations to the circuit illustrated in FIG. 2Amay be made without departing from the spirit or scope of the presentdisclosure as set forth in the claims provided below. For example,although a LIN driver is shown, the techniques described herein may beapplied to any low side driver circuit, and further, may be used in bothsides of a push-pull driver circuit.

What is claimed is:
 1. A driver circuit, comprising: a driver transistorhaving a gate terminal; a first circuit operable in response to a firststate of a signal to generate a gate charging current for application tothe gate terminal; and a second circuit operable in response to a secondstate of the signal to generate a gate discharging current forapplication to the gate terminal; wherein said gate charging currentcomprises a sum of a first exponentially decreasing current and a firstconstant current; and wherein said gate discharging current comprises asum of a second exponentially decreasing current and a second constantcurrent; a first capacitor wherein said first constant current isapplied to said first capacitor; and a clamping transistor selectivelycoupled in parallel to said first capacitor to generate a charge acrosssaid first capacitor for generating said first exponentially decreasingcurrent.
 2. The driver circuit as set forth in claim 1, wherein saidfirst circuit comprises a first switch actuated by the first state ofthe signal to pass the first constant current toward the gate terminal.3. The driver circuit as set forth in claim 2, wherein said firstcapacitor configure to be charge during the second state of the signaland discharged during the first state of the signal to generate thefirst exponentially decreasing current.
 4. The driver circuit as setforth in claim 2, wherein said first switch is further operable to passthe first exponentially decreasing current toward the gate terminal. 5.The driver circuit as set forth in claim 1, wherein said second circuitcomprises a second switch actuated by the second state of the signal togenerate the second constant current toward a ground node.
 6. The drivercircuit as set forth in claim 1, wherein said second circuit comprises athird switch actuated by the second state of the signal to generate thesecond exponentially decreasing current.
 7. The driver circuit as setforth in claim 6, wherein said second circuit further comprises a secondcapacitor that is charged during the second state of the signal togenerate the second exponentially decreasing current.
 8. The drivercircuit as set forth in claim 1, wherein the first exponentiallydecreasing current commences coincident with said first state of thesignal.
 9. The driver circuit as set forth in claim 1, wherein thesecond exponentially decreasing current commences coincident with saidsecond state of the signal.
 10. An integrated driver circuit,comprising: charging circuitry operable to receive a first chargingcurrent and generate a second charging current; discharging circuitryoperable to receive a first discharging current and generate a seconddischarging current; and an output transistor operable to receive a gatecurrent, wherein during a charging phase, said gate current comprisessaid first charging current and said second charging current, andwherein during a discharging phase, said gate current comprises saidfirst discharging current and said second discharging current; whereinduring said charging phase, said second charging current dissipates suchthat said gate current substantially comprises said first chargingcurrent; and wherein during said discharging phase, said seconddischarging current dissipates such that said gate current substantiallycomprises said first discharging current.
 11. The integrated drivercircuit as set forth in claim 10, wherein said second charging currentcommences coincident with said discharging phase.
 12. The integrateddriver circuit as set forth in claim 10, wherein said second dischargingcurrent commences coincident with said discharging phase.
 13. Theintegrated driver circuit as set forth in claim 10, wherein saidcharging circuitry comprises a first capacitor selectively coupled inparallel with a clamping transistor.
 14. The integrated driver circuitas set forth in claim 10, wherein said discharging circuitry comprises asecond capacitor operable to generate said second discharging current.15. The integrated driver circuit as set forth in claim 10, wherein saidsecond charging current dissipates such that said gate current achievesa smooth reduction in charge current.
 16. The integrated driver circuitas set forth in claim 10, wherein said second discharging currentdissipates such that said gate current achieves a smooth reduction indischarge current.
 17. The integrated driver circuit as set forth inclaim 10, wherein said gate current alternates between said chargingphase and said discharging phase.
 18. The integrated driver circuit asset forth in claim 10, wherein said first charging current is a constantcurrent.
 19. The integrated driver circuit as set forth in claim 10,wherein said first discharging current is a constant current.
 20. Adriver circuit, comprising: a driver transistor having a gate terminal;a first circuit comprising a first capacitor coupled to a firsttransistor and a first switch, said first circuit operable to receive afirst constant current and generate a first exponentially decreasingcurrent; a second switch operable to couple said first circuit to saidgate terminal to apply a gate charging current to said gate terminal; asecond circuit coupled to said gate terminal, said second circuitcomprising a third switch and a second capacitor, said second circuitoperable to generate a second exponentially decreasing current; and afourth switch coupled to said gate terminal and said second circuitry,wherein said third and fourth switches are operable to apply a gatedischarging current to said gate terminal; wherein said gate chargingcurrent comprises a sum of said first exponentially decreasing currentand said first constant current; and wherein said gate dischargingcurrent comprises a sum of said second exponentially decreasing currentand a second constant current.
 21. The driver circuit as set forth inclaim 20, further comprising a reference current generator.
 22. Thedriver circuit as set forth in claim 20, further comprising a firstcurrent mirror coupled to said second circuit and said fourth switch.23. The driver circuit as set forth in claim 22, wherein said firstcurrent mirror is operable to generate said second constant current. 24.The driver circuit as set forth in claim 20, further comprising a secondcurrent mirror coupled to said first circuit and said second switch. 25.The driver circuit as set forth in claim 24, wherein said second currentmirror is operable to generate said first constant current.
 26. Thedriver circuit as set forth in claim 20, further comprising a gateresistor coupled to said gate terminal.
 27. The driver circuit as setforth in claim 20, further comprising a third capacitor coupled to saidgate terminal, said third capacitor coupled in parallel with said secondcircuit.
 28. The driver circuit as set forth in claim 20, furthercomprising a second transistor coupled to said gate terminal.
 29. Thedriver circuit as set forth in claim 28, further comprising a secondresistor coupled in series with said second transistor, said secondresistor and second transistor coupled in parallel with said secondcircuit.
 30. The driver circuit as set forth in claim 20, furthercomprising an output bus coupled to a source terminal of said drivertransistor.
 31. The driver circuit as set forth in claim 30, furthercomprising a first diode coupled between said source terminal and saidoutput bus.
 32. The driver circuit as set forth in claim 30, furthercomprising a second diode and pull-up resistor coupled in series betweensaid output bus and a voltage source.
 33. The driver circuit as setforth in claim 20, wherein said first circuit further comprises a fourthresistor coupled to said first capacitor.
 34. The driver circuit as setforth in claim 20, wherein said second circuit further comprises a fifthresistor coupled to said second capacitor.
 35. A method, comprising:generating a first exponentially decreasing current in response to afirst state of a signal; generating a second exponentially decreasingcurrent in response to a second state of the signal; applying a chargingcurrent at a gate terminal of a driver transistor, wherein said chargingcurrent comprises a sum of a first constant current and said firstexponentially decreasing current; and applying a discharging current atsaid gate terminal of said driver transistor, wherein said dischargingcurrent comprises a sum of a second constant current and said secondexponentially decreasing current; wherein generating said firstexponentially decreasing current comprises applying said first constantcurrent to a first capacitor selectively coupled in parallel with aclamping transistor to generate a charge across said first capacitor.36. The method as set forth in claim 35, wherein generating said secondexponentially decreasing current comprises applying current drawn fromsaid gate terminal across a second capacitor.